They use the whole wafer for a chip (wafer scale). The WSE-3 chip is optimized for sparse linear algebra ops, used 5nm TSMC process.

Their idea is to have 44 GB SRAM per chip. SRAM is _very_expensive_ compared to DRAM (about two orders of magnitude).

It's easy to design larger chip. What determines the price/performance ratio are things like

- performance per chip area.

- yield per chip area.